Integrated circuits, such as digital signal processors (DSPs), use on-chip memory (memory module) to store information to be processed. The on-chip memory comprises, for example, an array of static random access memory cells or alternatively dynamic random access memory cells. The memory cells are connected to wordlines travelling in one direction and to bitlines travelling in another direction. Dynamic memory cells comprise a storage capacitor and at least one access transistor. The charge stored in the storage capacitor is indicative of the information stored (e.g., logic 0 or logic 1). Due to leakage effects the charge in the storage capacitor dissipates over time. The stored charge, therefore, has to be refreshed periodically to ensure that the memory cell maintains the correct information during the operation of the IC.
In some applications, a dual port memory module, is used. A dual port memory module includes first and second ports through which the memory cells can be accessed. Each port includes signal lines for receiving address, data and control signals. Each port, for example, includes an address decoder which selects a particular wordline or row of memory cells within the memory cell array. The memory cells are connected to both access ports by two separate wordlines and two separate bitlines.
The memory cells of the array must be refreshed after a specified time (e.g., retention time). However, the refresh cycle may coincide with the occurrence of an access request to the memory cell array through either one of the access ports. Conventionally, accesses to the memory module are halted until the refresh cycle is completed, which adversely impacts performance of the system.
From the foregoing discussion, there is a desire to provide a multi-port memory module in which the adverse impact on system performance by the refresh cycle is reduced.
The invention relates generally to ICs with a memory module. In particular, the invention relates to efficiently refreshing a multi-port memory module. In one embodiment, the memory modules include first and second ports. A control block manages the memory accesses and refresh requests. In one embodiment, the control block includes a contention detection circuit that monitors the memory access requests through the access ports as well as the refresh operations. A refresh counter provides the sequence of addresses of rows of memory cells that are to be refreshed. The addresses of memory accesses rows are provided through the access ports. The address decoder within each port activates the row either for a refresh or for a memory access. The contention circuit ensures that a refresh operation is allocated to a port which is not used for a memory access at the same time.